Minutes, IBIS Quality Committee

23 June 2009

11-12 AM EST (8-9 AM PST)

ROLL CALL
  Adam Tambone
* Anders Ekholm, Ericsson
  Barry Katz, SiSoft
  Benny Lazer
  Benjamin P Silva
  Bob Cox, Micron
* Bob Ross, Teraspeed Consulting Group
  Brian Arsenault
  David Banas, Xilinx
* Eckhard Lenski, Nokia Siemens Networks
  Eric Brock
* Guan Tao, Huawei Technologies
  Gregory R Edlund
  Hazem Hegazy
  Huang Chunxing, Huawei Technologies
  John Figueroa
  John Angulo, Mentor Graphics
  Katja Koller, Nokia Siemens Networks
  Kevin Fisher
  Kim Helliwell, LSI Logic
  Lance Wang, IOMethodology
  Lynne Green
* Mike LaBonte, Cisco Systems
  Mike Mayer, SiSoft
  Moshiul Haque, Micron Technology
  Muniswarareddy Vorugu, ARM Ltd
* Pavani Jella, TI
  Peter LaFlamme
  Randy Wolff, Micron Technology
  Radovan Vuletic, Qimonda
  Robert Haller, Enterasys
  Roy Leventhal, Leventhal Design & Communications
  Sherif Hammad, Mentor Graphics
  Todd Westerhoff, SiSoft
  Tom Dagostino, Teraspeed Consulting Group
  Kazuyoshi Shoji, Hitachi
  Sadahiro Nonoyama
  Liqun, Huawei

Everyone in attendance marked by *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

Call for patent disclosure:

- No one declared a patent.

AR Review:

- Mike fix font and reference issues in IQ specification identified by Anders
  - TBD

New items:

Mike will present to Motorola Tuesday June 30 on IBIS Quality
- The time slot conflicts with IQ
- There will be no IQ meeting that day

Continuation of Anders Eckholm's review of the IQ 1.1 specification:

From Anders' email:
    3.2.1
    First Bullet, No connects must be represented with NC. Why? 
- Mike: Some tools require every pin to be present in the IBIS file
- Bob: The pin is in the layout, and the tool finds a mismatch

From Anders' email:
    3.2.1
    Same bullet the wording pin map can be confusing in relation to the
    keyword [Pin Mapping] ?
- We changed to "[Pin] section"

From Anders' email:
    3.2.1
    Bullet 5 Special pins ...... even if they are marked NC. How does
    this relate to bullet 1.
- Mike: Vref pins, for example
  - Sometimes we need to see the waveforms for these pins
  - Some tools will shows waveforms only if they are Input
- Bob: We use Terminator models
  - Analog tools will look at it for net integrity
- Mike: JEITA wanted these checks removed, but we pushed back

From Anders' email:
    3.2.1
    2 next bullets, Power and Gnd, where should this be indicated signal
    name or model name ?
- We added "model name" to the first 3 bullets

From Anders' email:
    3.2.2 
    For a level 2 model pin parasitics are optional, but they are mandatory
    for a level 3....  okay but I feel pin mapping is important even for
    waveform simulation.
- Anders: This means [Pin] RLC, not [Pin Mapping]
- Mike: Pin RLC is needed for exact pin-to-pin skew calculation
  - Without that the [Package] still gives RLC for waveform simulation
- Bob: It is difficult to categorize between time and voltage domains
  - [Package] is the fallback where [Pin] RLC is absent
  - Kim Heliwell used diagonal matrix values to get [Pin] RLC
  - Would like to change this to level 2, but it is OK as is.
- Pavani: Requiring RLC for level 2 would be no problem
- We left 3.2.2 as is

3.3.2.	{LEVEL 2}  [Diff Pin] referenced pin models matched
- Anders: P and N pins are never really identical
- Bob: Some tools have an idiosynchracy about showing waveforms where
  two pins use the same model and one is inverted
- Anders: This asks people to explain why they did it correctly.
- Mike showed minutes of previous meetings in which this check was discussed
- Mike: Should we drop this check altogether?
  - Anders: No but it should require the opposite of what it does
- No change made, need to discuss this more

Meeting ended at 12:06 PM Eastern Time.